The present invention relates generally to integrated circuit devices, and, more particularly, to an apparatus and method for implementing multiple memory redundancy using a delay-tracking clock.
Static Random Access Memories (SRAMs) are memory elements that store data in the form of complementary low voltage and high voltage at opposite sides of the memory cell. An SRAM retains the memory value therein so long as power is applied to the circuit, unlike dynamic random access memory (DRAM) that must be periodically refreshed in order for the data to be maintained therein. Conventionally, if the “true” node of an SRAM is read as a high voltage, then the value of the SRAM cell is logical one. Conversely, if the true node is read as a low voltage, the value of the SRAM cell is logical zero.
Due to the high degree of miniaturization possible today in semiconductor technology, the size and complexity of designs that may be implemented in hardware has increased dramatically. This has made it technologically feasible and economically viable to develop high-speed, application specific architectures featuring a performance increase over previous architectures. Process scaling has been used in the miniaturization process to reduce the area needed for both logic functions and memory (such as SRAM) in an effort to lower the product costs.
In order to improve the yield of high-speed, high-density SRAM products, redundant elements are incorporated into the devices. These redundant elements may include for example, row elements, column elements, or both. Generally speaking, the larger the SRAM device, the more repair actions are likely needed for yield improvement. With the availability of multiple row and column repair actions, yield is significantly improved since there is greater flexibility in dealing with the various defect mechanisms. However, one problem associated with more complicated, multiple repair actions is the increase in time taken to perform the repair actions. With conventional static redundancy decoding schemes, multiple repair actions can conceivably place limit on the access time of the memory device and, as such, adversely affect system performance.
Accordingly, it would be desirable to be able to implement a multiple word redundancy repair scheme in a manner that minimizes the impact on device performance.